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2010 year - 2010 year

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417.00 zł - 418.00 zł

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Wafer-level Testing and...

Wafer-level Testing and Test During Burn-in for Integrated Circuits

Author: Krishnendu Chakrabarty
Sudarshan Bahukudumbi
Publishing date: 2010
Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing. Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constraints. Moreover, this unique book helps practitioners address the issue of enabling next generation products with previous generation testers. Practitioners also find expert
417.90 zł